ad557?pecifications model min typ max unit resolution 8 bits relative accuracy 0 c to 70 c 1/2 1 lsb output ranges 0 to 2.56 v current source 5 ma sink internal passive pull-down to ground 2 output settling time 3 0.8 1.5 s full-scale accuracy 4 @ 25 c 1.5 2.5 lsb t min to t max 2.5 4.0 lsb zero error @ 25 c 1 lsb t min to t max 3 lsb monotonicity 5 t min to t max guaranteed but not tested digital inputs t min to t max input current 100 a data inputs, voltage bit on?ogic ? 2.0 v bit on?ogic ? 0 0.8 v control inputs, voltage on?ogic ? 2.0 v on?ogic ? 0 0.8 v input capacitance 4 pf timing 6 t w strobe pulsewidth 225 ns t min to t max 300 ns t dh data hold time 10 ns t min to t max 10 ns t ds data setup time 225 ns t min to t max 300 ns power supply operating voltage range (v cc ) 2.56 volt range 4.5 5.5 v current (i cc )1 5 2 5 m a rejection ratio 0.03 %/% power dissipation, v cc = 5 v 75 125 mw operating temperature range 0 70 c notes 1 relative accuracy is defined as the deviation of the code transition points from the ideal transfer point on a straight line from the offset to the full scale of the device. see ?easuring offset error?on the ad558 data sheet. 2 passive pull-down resistance is 2 k ? . 3 settling time is specified for a positive-going full-scale step to 1/2 lsb. negative- going steps to zero are slower, but can be improved with an external pull-down. 4 the full-scale output voltage is 2.55 v and is guaranteed with a 5 v supply. 5 a monotonic converter has a maximum differential linearity error of 1 lsb. 6 see figure 7. specifications shown in boldface are tested on all production units at electrical test. specifications subject to change without notice. (@ t a = 25 c, v cc = 5 v unless otherwise noted) pin configurations dip v out sense b cs ce 10 9 13 12 11 16 15 14 8 1 2 3 4 7 6 5 top view (not to scale) ad557 gnd v out sense a v out bit 7 bit 6 bit 5 +v cc gnd bit 4 bit 3 bit 2 (msb) bit 1 (lsb) bit 8 plcc 20 19123 4 5 6 7 8 9 10 11 12 13 top view (not to scale) pin 1 identifier 18 14 15 16 17 bit 6 bit 5 nc bit 4 bit 3 v out sense b gnd nc gnd +v cc ad557 v out sense a bit 7 v out nc bit 8 (lsb) nc = no connect bit 2 (msb) bit 1 nc ce cs rev. b C2C ordering guide temperature package package model range description option ad557jn 0 c to 70 c plastic dip n-16 ad557jp 0 c to 70 c plastic leaded chip carrier p-20a absolute maximum ratings * v cc to ground . . . . . . . . . . . . . . . . . . . . . . . . . . . 0 v to 18 v digital inputs (pins 1?0) . . . . . . . . . . . . . . . . . . . 0 v to 7.0 v v out . . . . . . . . . . . . . . . . . . . . . . . indefinite short to ground momentary short to v cc power dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . 450 mw storage temperature range n/p (plastic) packages . . . . . . . . . . . . . . . . ?5 c to +100 c lead temperature (soldering, 10 sec) . . . . . . . . . . . . . 300 c thermal resistance junction to ambient/junction to case n/p (plastic) packages . . . . . . . . . . . . . . . . . . 140/55 c/w * stresses above those listed under absolute maximum ratings may cause perma- nent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability.
ad557 rev. b C3C connecting the ad557 the ad557 has been configured for low cost and ease of appli- cation. all reference, output amplifier and logic connections are made internally. in addition, all calibration trims are performed at the factory assuring specified accuracy without user trims. the only connection decision to be made by the user is whether the output range desired is unipolar or bipolar. clean circuit board layout is facilitated by isolating all digital bit inputs on one side of the package; analog outputs are on the opposite side. unipolar 0 v to 2.56 v output range figure 2 shows the configuration for the 0 v to 2.56 v full- scale output range. because of its precise factory calibration, the ad557 is in tended to be operated without user trims for gain and offset; therefore, no provisions have been made for such user trims. if a small increase in scale is required, however, it may be accomplished by slightly altering the effective gain of the output buffer. a resistor in series with v out sense will increase the output range. note that decreasing the scale by putting a resistor in series with gnd will not work properly due to the code- dependent currents in gnd. adjusting offset by injecting dc at gnd is not recommended for the same reason. 16 15 14 13 output amp v out v out sense a v out sense b gnd figure 2. 0 v to 2.56 v output range bipolar ?.28 v to +1.28 v output range the ad557 was designed for operation from a single power supply and is thus capable of providing only a unipolar 0 v to 2.56 v output range. if a negative supply is available, bipolar output ranges may be achieved by suitable output offsetting and scaling. figure 3 shows how a 1.28 v output range may be achieved when a ? v power supply is available. the offset is provided by the ad589 precision 1.2 v reference which will operate from a 5 v supply. the ad711 output amplifier can provide the necessary 1.28 v output swing from 5 v supplies. coding is complementary offset binary. ?.2v 4.7k 0.01f ad589 ?v v in ad557 v out = 0v to 2.56v 5k 5k 4.53k 1.5k 500 bipolar offset adjust 0.01f 0.01f ad711 ?v +5v v o +1.28 to ?.27 input code 00000000 10000000 11111111 v out +1.28v 0v ?.27v figure 3. bipolar operation of ad557 from 5 v supplies circuit description the ad557 consists of four major functional blocks fabricated on a single monolithic chip (see figure 1). the main d/a con- verter section uses eight equally weighted laser-trimmed current sources switched into a silicon-chromium thin-film r/2r resistor ladder network to give a direct but unbuffered 0 mv to 400 mv output range. the transistors that form the dac switches are pnps; this allows direct positive-voltage logic interface and a zero-based output range. bit1 (msb) bit8 (lsb) gnd cs ce control inputs digital input data (bus) + v cc l 2 l control logic 8-bit voltage-switching d-to-a converter output amp control amp band-gap reference v out v out sense a v out sense b l 2 l latches gnd figure 1. functional block diagram the high-speed output buffer amplifier is operated in the nonin- verting mode with gain determined by the user-connections at the output range select pin. the gain-setting application resistors are thin film laser trimmed to match and track the dac resistors and to assure precise initial calibration of the out- put range, 0 v to 2.56 v. the amplifier output stage is an npn transistor with passive pull-down for zero-based output capability with a single power supply. the internal precision voltage reference is of the patented band-gap type. this design produces a reference voltage of 1.2 v and thus, unlike 6.3 v temperature-compensated zeners, may be operated from a single, low-voltage logic power supply. the microprocessor interface logic consists of an 8-bit data latch and control circuitry. low power, small geometry and high speed are advantages of the i 2 l design as applied to this section. i 2 l is bipolar process compatible so that the performance of the analog sections need not be compromised to prov ide on-chip logic capabilities. the control logic allows the latches to be operated from a decoded microprocessor address and write sig- nal. if the application does not involve a p or data bus, wiring cs and ce to ground renders the latches ?ransparent?for direct dac access. digital input code output binary hexadecimal decimal voltage 0000 0000 00 0 0 0000 0001 01 1 0.010 v 0000 0010 02 2 0.020 v 0000 1111 0f 15 0.150 v 0001 0000 10 16 0.160 v 0111 1111 7f 127 1.270 v 1000 0000 80 128 1.280 v 1100 0000 c0 192 1.920 v 1111 1111 ff 255 2.55 v
ad557 rev. b C4C timing and control the ad557 has data input latches that simplify interface to 8- and 16-bit data buses. these latches are controlled by chip enable ( ce ) and chip select ( cs ) inputs. ce and cs are inter- nally ?ored?so that the latches transmit input data to the dac section when both ce and cs are at logic ?.?if the application does not involve a data bus, a ?0?condition allows for direct operation of the dac. when either ce or cs go to logic ?,?the input data is latched into the registers and held until both ce and cs return to ?.?(unused ce or cs inputs should be tied to ground.) the truth table is given in table i. the logic function is also shown in figure 6. v out 7.5 5.0 2.5 00h 80h ffh ad557 input code figure 6. ad557 input code vs. level shifted output in a false ground configuration table i. ad557 control logic truth table latch input data ce cs dac data condition 0 0 0 0 ?ransparent 1 0 0 1 ?ransparent 0 g 0 0 latching 1 g 0 1 latching 00 g 0 latching 10 g 1 latching x 1 x previous data latched x x 1 previous data latched notes x = does not matter g = logic threshold at positive-going transition in a level-triggered latch such as that used in the ad557, there is an interaction between the data setup and hold times and the width of the enable pulse. in an effort to reduce the time required to test all possible combinations in production, the ad557 is tested with t ds = t w = 225 ns at 25 c and 300 ns at t min and t max , with t dh = 10 ns at all temperatures. failure to comply with these specifications may result in data not being latched properly. figure 7 shows the timing for the data and control signals, ce and cs are identical in timing as well as in function. data inputs cs or ce dac v output 0.8v 0.8v 2.0v 2.0v 1/2 lsb t w t settling t dh t w = strobe pulsewidth = 225ns min t dh = data hold time = 10ns min t ds = data setup time = 225ns min t settling = dac settling time to 1/2 lsb t ds figure 7. ad557 timing applications grounding and bypassing all precis ion converter products require careful application of good g rounding practices to maintain full rated performance. because the ad557 is inte nded for application in microcom- puter systems where digital noise is prevalent, special care must be taken to assure that its inherent precision is realized. the ad557 has two ground (common) pins; this minimizes ground drops and noise in the analog signal path. figure 4 shows how the ground connections should be made. it is often advisable to maintain separate analog and digital grounds throughout a complete system, tying them common in one place only. if the common tie-point is remote and acciden- tal disconnection of that one common tie-point occurs due to card removal with power on, a large differential voltage between the two commons could develop. to protect devices that inter- face to both digital and analog parts of the system, such as the ad557, it is recommended that common ground tie-points should be provided at each such device. if only one system ground can be connected directly to the ad557, it is recom- mended that analog common be selected. 16 15 14 13 output amp v out v out sense a v out sense b gnd 12 11 gnd +v cc 0.1f to system gnd to system gnd (see text) to system v cc r l figure 4. recommended grounding and bypassing using a ?alse?ground many applications, such as disk drives, require servo control voltages that swing on either side of a ?alse?ground. this ground is usually created by dividing the 12 v supply equally and calling the midpoint voltage ?round. figure 5 shows an easy and inexpensive way to implement this. the ad586 is used to pro vide a stable 5 v reference from the system? 12 v supply. the op amp shown likewise operates from a single (12 v) supply available in the system. the resulting out- put at the v out node is 2.5 v around the ?alse?ground point of 5 v. ad557 input code vs. v out is shown in figure 6. ad557 100k 100k 100k 200k 1/4 lm324 v out ad586 v in 2 12v 5v false ground 6 4 figure 5. level shifting the ad557 output around a false ground
ad557 rev. b C5C outline dimensions dimensions shown in inches and (mm). n-16 (plastic) package 0.87 (22.1) max 0.25 (6.35) 0.31 (7.87) 0.035 (0.59) 0.125 (3.18) min 0.18 (4.57) 0.018 (0.46) 0.033 (0.84) 0.1 (2.54) 0.3 (7.62) 0.011 (0.28) 0.18 (4.57) max p-20a (plcc) package no.1 pin identifier top view 0.390 0.005 (9.906 0.125) sq 0.353 0.003 (8.966 0.076) sq 0.045 0.003 (1.143 0.076) 0.020 (0.51) max 0.02 (0.51) max 0.050 (1.27) 0.173 0.008 (4.385 0.185) 0.105 0.015 (2.665 0.375) 0.020 (0.51) min 0.035 0.01 (0.89 0.25) 0.029 0.003 (0.737 0.076) 0.017 0.004 (0.432 0.101) 0.025 (0.64) min 0.060 (1.53) min
printed in u.s.a. c00512aC0C1/01 (rev. b) location page data sheet changed from rev. a to rev. b. changes to monotonicity section of spec. page . . . . . . . . . 2 ad557 revision history rev. b C6C
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